The present invention relates to computer memory, and more specifically, to solid state drive (SSD) memory.
SSD is may be used in place of hard disk drives (HDDs) to provide higher performance and reduce mechanical reliability issues. An SSD includes a high-speed interface connected to a controller chip and a plurality of storage, or memory, elements. The controller chip translates a high speed protocol received over the high speed interface into the protocol required by the storage elements, which include solid state memory devices (for example, semiconductor devices). An example of a type of SSD includes flash devices. The controller controls the occurrence of read and erase (i.e., program/erase cycles, or PE cycles) events in the storage elements. The storage elements in the SSD comprise a plurality of blocks, which are the smallest erasable units in the memory. The blocks are subdivided into pages, which are the smallest readable units of the memory, and pages are subdivided into sectors. In a PE cycle, all the pages in a block are erased and then some, if not all, of the pages in the block are subsequently programmed.
An issue for SSDs is the reliability of the storage elements over the life of the SSD. Over time, relatively high gate voltages applied to the storage elements during PE cycles in the SSD may cause cumulative permanent changes to the storage element characteristics. Charge may become trapped in the gate oxide of the storage elements through stress-induced leakage current (SILC). As the charge accumulates, the effect of programming or erasing a storage element becomes less reliable and the overall endurance of the storage element decreases. Additionally, an increasing number of PE cycles experienced by a storage element decreases the storage element's data retention capacity, as high voltage stress causes charge to be lost from the storage element's floating gate.
One method of prolonging the endurance and data retention capacities of a SSD is wear leveling. Wear leveling attempts to distribute PE cycling equally among all storage elements in the SSD so that all storage elements wear at similar rates and the overall lifespan of the SSD is prolonged. Another means of prolonging the endurance and data retention capacities of an SSD is using a set of storage elements including a hybrid memory array that is a mixture of higher endurance memory (i.e., single-level cell, or SLC), and lower endurance memory (i.e. multi-level cell, or MLC). In such a hybrid memory array, higher frequency accesses are mapped to addresses in the higher endurance memory and lower frequency accesses are mapped to addresses in the lower endurance memory. Such a scheme prolongs the lifetime of the overall flash memory array.